1. Field of the Invention
This invention relates generally to the field of magnetic storage devices and specifically to read/write head circuitry.
2. Background Art
In magnetic recording devices, such as magnetic disks and tapes, a recording head is used to read and write information to and from the magnetic surface. In a typical rotating medium based storage system, data is stored on magnetic disks in a series of concentric "tracks." These tracks are accessed by a read/write head that detects variations in the magnetic orientation of the disk surface. The read/write head moves back and forth radially on the disk under control of a head-positioning servo mechanism so that it can be selectively positioned over a selected one of the tracks. Once in position over a track, the servo mechanism causes the head to trace a path that follows the center line of the selected track.
A simple configuration of a conventional inductive recording head is illustrated in FIG. 1. The inductive recording head consists of a slit toroid (10) made up of high permeability magnetic material and wound by several conductor turns (11). The toroid contains a gap (12) which is positioned over data tracks (13) on the magnetic recording surface (14).
To record, a current is generated through the conductor windings, altering the magnetic field in the toroid. At the location of the gap, the amplitude of the magnetic field is large enough to record on the magnetic material of the storage device to a sufficient depth. The amplitude of the magnetic field falls off sharply away from the gap. By manipulating the current through the conductor windings, the magnitude and direction of the magnetic flux at the location of the gap can be modulated in such a fashion as to encode information into the magnetic surface of the storage device. A pattern of external and internal fields are created as the head and recording surface are moved relative to each other. These patterns are similar to a series of bar magnets of changing polarities. The polarity transitions are then readable as transitions in the magnetic flux at the recording surface. In read mode, as the magnetic storage surface moves across the gap in the head, the magnetic field of the storage surface is detected at the gap, and a voltage is induced in the coil proportional to the rate of change of the flux. The read circuit then amplifies this analog voltage signal. The amplified read-back voltage signal would then be processed and decoded by the read channel circuitry into digital data.
Due to the inductive characteristics of the head and the circuit and stray capacitance of the read/write circuitry, the write current that can be generated through the head are prone to ringing effects. An equivalent circuit representing the impedance at the terminals coupling the read/write circuitry to the head is shown in FIG. 2. Nodes HX and HY represent the I/O terminals of the read/write circuitry for operating on a single head. An inductance, L, representing the head inductance, is coupled between terminals HX and HY. Coupled in parallel with the inductance are capacitance C, representing the circuit and stray capacitance, and current source IW, representing the write current. Assuming a unit step current input at time t=0, the inductor current is given by the equation: EQU i.sub.L (t)=1-2 cos (.omega..sub.o t) (equation 1)
where .omega..sub.o.sup.2 =1/(LC). The ringing in the circuit results from the cosine element in the equation.
This ringing effect restricts the operating frequency range of the circuit. The write circuit can not change the current for the following data bits until this current has stabilized. For this reason the maximum operating frequency of the head circuitry is directly affected by the settling time of the inductor current. One way to reduce the ringing in the circuit is to introduce a damping resistance in parallel with the inductance. This shunt resistance introduces an exponential attenuation factor into the current equation that causes the ringing signal to decrease over time.
A standard damping scheme is illustrated in FIG. 3. FIG. 3 illustrates a simplified view of the write driving circuitry with a damping resistor (Rd) coupled between terminals HY and HX. This write driver is commonly known as an "H" bridge. Terminals HY and HX are each coupled to one terminal of the head inductor. NPN transistor Q1 has its collector coupled to the positive voltage supply and its base coupled through resistance R1 to the positive voltage supply. NPN transistor Q2 has its collector coupled to the positive voltage supply and its base coupled through R2 to the positive voltage supply. NPN transistors Q3 and Q4 are emitter coupled to the write current source. The base contacts of transistors Q3 and Q4 are coupled to WD and WD* (write data and write data*) signals respectively. The emitter of transistor Q1 and the collector of transistor Q3 are coupled to terminal HY. The emitter of transistor Q2 and the collector of transistor Q4 are coupled to terminal HX. The collectors of transistors Q31 and Q32 are coupled to the bases of transistors Q1 and Q2, respectively. The bases of transistors Q31 and Q32 are coupled to WD and WD*, respectively, and the emitters of Q31 and Q32 are coupled to respective current sources.
Transistors Q3 and Q4 are used to direct the write current. Transistors Q31 and Q32 selectively turn off Q1 or Q2 as required by Q3 and Q4. When signal WD* is high, the current flows from the positive voltage supply through transistor Q1 into terminal HY. The current then passes through damping resistor R.sub.d in parallel with the head inductor to terminal HX where it is directed by transistor Q4 to the write current source. In the alternative case, when signal WD is high, the write current passes through transistor Q2 to terminal HX, across the parallel resistance and inductance to terminal HY and down through transistor Q3.
An equivalent circuit model for the load at terminals HX and HY is shown in FIG. 4. The circuit of FIG. 4 is the same as the circuit of FIG. 2, except for the addition of the damping resistance, Rd, coupled between nodes HX and HY. The current equation for this circuit, assuming a unit step input at time t=0, is given by: EQU i.sub.L (t)=1-2(.omega..sub.o /.omega..sub.d)[e.sup.-.alpha.t cos (.omega..sub.d t-.phi.)] (equation 2)
where .omega..sub.o.sup.2 =1/(LC), .alpha.=1/(2RC), .omega..sub.d.sup.2 =.omega..sub.o.sup.2 -.alpha..sup.2, and .phi.=tan .sup.-1 (.alpha./.omega..sub.d).
For this scheme, the magnitude of the ringing term is a function of the ratio between the LC time constant and the RC time constant, as is the phase. The oscillating frequency of the ringing term is determined by the LC and RC time constants and approaches zero as .alpha. approaches .omega..sub.d. The attenuation of the ringing term is entirely dependent on the RC time constant. It is therefore desirable to have a small damping resistance to facilitate rapid settling of the current. Taking the limit of equation 2 as Rd approaches infinity generates equation 1, which is consistent with what is expected.
The circuit described above, with a simple damping resistor coupled in parallel with the head inductance, is effective in providing damping during the write process. However, the small damping resistance can be counter-productive during a read operation, because it may serve to overly attenuate the analog read signal and cause reading errors.
There are several schemes in the prior art for removing the resistance from the circuit during a read operation. One such scheme is the Schottky isolated damping scheme illustrated in FIG. 5. The circuit shown in FIG. 5 would replace the damping resistance in FIG. 3. In this scheme resistor 300, having a resistance of Rd/2, is coupled between node 304 and terminal HY. Resistor 301, also having a resistance of Rd/2, is coupled between node 305 and terminal HX. Schottky diode 303 is coupled between node 304 and 305 such that it will conduct current from node 304 to node 305 when its forward bias voltage reaches the diode turn-on voltage, V.sub.d (typically 0.5 volts). Schottky diode 302 is coupled between nodes 304 and 305 such that it will conduct current from node 305 to node 304 when its forward bias voltage reaches V.sub.d.
With this damping scheme, the diodes act as an open circuit for a potential difference between terminal HX and terminal HY of magnitude less than V.sub.d. The resistance between terminals HX and HY for the circuit of FIG. 3 is effectively infinite for the voltage window of (-V.sub.d &lt;V.sub.HY-HX &lt;V.sub.d). Outside of this window, the circuit acts as a resistance of R.sub.d in series with a constant voltage source of V.sub.d (assuming an ideal diode). Thus, for read voltages on the order of a few millivolts at most, the damping circuit is cut off.
FIG. 6 illustrates the voltage-current characteristics of the circuit of FIG. 5. The vertical axis represents the potential difference between terminal HY and terminal HX, V.sub.HY-HX. The horizontal axis represents the current I.sub.R shown in FIG. 5 as running from node 305 to terminal HX. Assuming ideal diodes, the voltage versus current function is linear with a slope of R.sub.d and voltage intercept of minus V.sub.d for currents less than zero. At I.sub.R =0, the function achieves an infinite slope for the voltage range from minus V.sub.d to V.sub.d. For positive current values, the function is described by a line of slope R.sub.d with a voltage intercept of V.sub.d. As shown, for the ideal case and for potential differences having magnitudes less than V.sub.d, the circuit behaves as an open circuit, and, as stated with reference to FIG. 5, for potential differences with magnitudes greater than V.sub.d, the circuit behaves as a resistor of value R.sub.d in series with a voltage source of magnitude V.sub.d.
A disadvantage of the circuit of FIG. 5 is the existence of non-ideal elements in the diode structure, such as resistance and capacitance associated with the layout of the diode. A compromise must be made between the diode size and the resultant resistance and capacitance of the diode structure. Another disadvantage is the inherent diode turn-off and subsequent loss of attenuation at lower levels of ring voltage.
Another damping circuit of the prior art is the switched Schottky clamp circuit shown in FIG. 7. Resistor 300 of resistance Rd/2 is coupled between terminal HY and node 503. Resistor 301, also of resistance Rd/2, is coupled between terminal HX and node 504. NPN Schottky transistor QS1 is coupled between node 503 and 504, with its emitter coupled to node 503, its collector coupled to node 504 and its base coupled to a control node 502. NPN Schottky transistor QS2 is also coupled between 503 and 504, with its emitter coupled to node 504, its collector coupled to node 503 and its base coupled to control node 502. Dependent current source 500 is coupled between V.sub.dd and node 502. The value of the current flowing through current source 500 is dependent on the current flowing through current source 501 coupled between V.sub.dd and node 505.
Schottky transistors QS1 and QS2 act as standard NPN transistors with a Schottky diode coupled between the base and the collector. For V.sub.bc (base-collector voltage) less than V.sub.d, the Schottky diode is nonconducting. However, when Vbc reaches the Schottky diode turn-on voltage (approx. 0.5 volts), the Schottky diode begins conducting current between the base and the collector of the transistor. This configuration prevents the transistor from going into the saturation region that is typically around V.sub.ce (collector-emitter voltage)=0.2 volts. Rather than entering into the saturation region, the minimum V.sub.ce is established by the Schottky turn on voltage and the base-emitter voltage when the transistor is near saturation. Therefore the collector-emitter voltage is prevented from dropping down to saturation, and is restricted to: EQU V.sub.ce =V.sub.be -V.sub.d .apprxeq.0.8 volts-0.5 volts.apprxeq.0.3 volts
For the circuit of FIG. 7, when current source 500 is conducting current, the damping circuit performs as a resistor of value R.sub.d in series with a voltage source of value 0.3 volts. Transistor QS1 conducts current when terminal HX is at a higher potential than terminal HY, and transistor QS2 conducts current when terminal HY is at a higher potential than terminal HX. The voltage versus current characteristics of this circuit are similar to those shown in FIG. 6, with V.sub.d becoming V.sub.ce =0.3 volts. In read mode, current source 500 does not conduct current and therefore, transistors QS1 and QS2 are shut off, becoming an open circuit.
The circuit of FIG. 7 has advantages over the circuit of FIG. 5 in that during a write operation, the voltage range wherein the damping circuit shuts off is reduced from a 0.5 volt peak range to a 0.3 volt peak range. The disadvantages of the circuit of FIG. 7 are that it requires extra circuitry to implement and the circuit introduces an offset error term to the write current through the head that is equivalent to the current generated in current source 500. Also, although the turn off voltage range as been reduced by 40% over the circuit of FIG. 5, it is preferred that there be no turn-off region at all in the write mode.
The circuits of FIGS. 5 and 7 also have a further disadvantage. Sometimes it is desirable to have moderate damping during the read mode, since the analog read signal may also be subject to ringing effects. In this case, the damping resistance required may be much higher than that needed during a write operation.